Data signals in many types of high speed digital communication systems are transmitted without an accompanying clock signal. Receivers in these systems typically use clock recovery to extract or “recover” clock signals that are associated with the data signals. In phase-locked-loop (PLL)-based clock recovery systems, a clock signal is recovered from a data signal by locking the phase of an oscillator in the clock recovery system to the phase of edge transitions within the data signal. The recovered clock signals are typically used to provide timing information that enables receivers to accurately sample the data signals.
In a typical measurement application, the clock recovery system is included in a digital communication analyzer (DCA) where the recovered clock signal is used to strobe a sampler, enabling the data signal to be sampled and represented on a display. In other measurement applications, it is advantageous to characterize phase differences between the data signal and the recovered clock signal at time positions established by a trigger signal, to determine the phase error between the recovered clock signal and the data signal, time-referenced to the trigger signal. Time referencing the phase error to a trigger signal would enable the clock recovery system to acquire phase error measurements that are synchronized to external events such as modulation signals that are applied to the data signal. These types of phase error measurements are particularly useful in characterizing performance of phase locked loops and other systems.
Accordingly, there is a need for a clock recovery system that has the capability to measure the phase error between an applied data signal and a recovered clock signal, time-referenced to a trigger signal.